This invention relates generally to interface circuits for use in telecommunication systems and more particularly, it relates to a reset and synchronization interface circuit for use in a subscriber power controller integrated circuit which supplies power across the S interface of the Integrated Services Digital Network (ISDN).
In the field of telecommunications, use of digital signalling techniques in transmitting information over long distances is gaining more and more prominence for a wide range of communication, including voice, computer data and video data. Typically, the S or subscriber lines interface as referred to by the Consultative Committee for international Telegraphy and Telephony (CCITT) is used to interconnect ISDN terminal equipment to one or more network terminators such as a private branch exchange (PBX). A subscriber power controller (SPC) is used to convert the 40 volts delivered at the S interface into a stable, regulated 5 volt power supply for integrated circuits in the ISDN terminal equipment such as a phone or data generating equipment. Such a power controller is manufactured and sold by Advanced Micro Devices, Inc. of Sunnyvale, Calif. under part No. designated as Am7936. The subscriber power controller is an integrated circuit formed in a single-chip package and has as one of its capabilities to reset a digital subscriber controller, a microprocessor, and other integrated circuits in the terminal equipment upon detecting of a low voltage and to synchronize an internal free-running oscillator to be in synchronism with an external clock signal for use with other integrated circuits in the terminal equipment.
A reset and synchronization interface circuit of the present invention is provided as a part of the same subscriber power controller integrated circuit for performing such resetting and synchronizing functions so as to provide reset signals to other integrated circuits in the terminal equipment and to eliminate noise interference due to intermodulation hum. This result is achieved by the provision of a resetting means formed of a first comparator, a second comparator and an inverting network for generating a reset signal and a synchronizing means formed of a third comparator and a logic gate for generating a modified synchronizing signal.